The present invention generally relates to a logic operation circuit, and more particularly to a logic operation circuit, which is suitably built in a semiconductor memory for image processing.
Currently, a computer system such as a personal computer and a workstation has various functions for displaying graphic information, such as multiwindow display, popup menu, and scroll bar. However, an expansion and enrichment of graphic functions impose a heavy load on software and thereby reduce the operation speed. From this viewpoint, a hardware function called a raster operation or bit blt is employed.
A raster operation denotes a function in which a rectangular region formed in a display memory such as a frame buffer is designated for each individual bit, and information in the designated rectangular region is transferred to a destination region. In the raster operation, a logic operation such as an AND, OR and EOR operation is carried out with respect to bit information stored in the rectangular region and bit information stored in the destination region. Such a logic operation is employed for enabling cursor display and overlapping window operation.
The raster operation can be implemented by a hardware structure which includes a frame buffer and an operation circuit. The frame buffer is divided into a frame region and a window region. The frame region has a memory space corresponding to a screen of a display unit. The window region has a memory space used for arranging a plurality of windows without overlapping each other or for storing data for cursor display and icon display as necessary. Image data supplied from a host computer is transferred directly to the frame buffer and is then stored in a position in the frame region or window region. Source data S and destination data D are read out from the frame buffer, and are then supplied to a logic operation circuit. In accordance with an instruction supplied from the host computer, the logic operation circuit selects an operation circuit which performs a corresponding logic expression. The selected logic circuit performs the logic operation on the source data S and the destination data D. A result of the logic operation is written into a region in which the above destination data was stored. For example, in a case where the designated logic operation is an OR operation, a logic expression "S OR D.fwdarw.Q" is performed, and an operation result Q is written into the region in which the destination data D was stored.
However, the above logic operation circuit has disadvantages described below. Since the logic operation circuit is constituted by a wired logic circuit, the circuit is necessarily large in size. For this reason, it is difficult to provide the logic operation circuit on a memory chip. Further, the time it takes to perform a logic expression such as AND, OR and NOR, varies depending on the type of logic expression. This is because the signal transfer characteristic of one operation circuit of the logic operation circuit is not the same as that of another operation circuit. The above circumstance arises from the circuit structure of a logic circuit and the number of gates thereof.